FIG. 1 illustrates a conventional EEPROM memory array. A section 10 of eight EEPROM cells is illustrated in detail. Conventional EEPROM memory cells have a byte select transistor 12 as illustrated in FIG. 1 which selects or de-selects eight EEPROM cells at a time. Each EEPROM cell of the eight EEPROM cells in section 10 have a single drain select transistor 14 and a single floating gate transistor 16. Therefore, the detailed illustration of section 10 in FIG. 1 contains eight drain select transistors 14 which are respectively coupled serially to eight floating gate transistors 16 to make eight EEPROM cells. The drain electrodes of the drain select transistors 14 are coupled to bit lines 20 as illustrated in FIG. 1. The source electrodes of the floating gate transistor 16 are all coupled together to a common source 22 as illustrated in FIG. 1. Vertical and horizontal selection of memory cells is performed respectively using the vertical select 18 and the horizontal select 24. Both the vertical select 18 and the horizontal select 24 are coupled to the byte select transistor 12.
The conventional EEPROM device of FIG. 1 requires extremely high drain voltages in order to properly operate. Specifically, drain voltages applied through the transistors 14 to the floating transistors 16 are typically on the order of 10-16 volts in order to enable EEPROM tunneling effects. In order to properly handle this large voltage and the higher electric fields/currents associated with this larger voltage range, the drain select transistors 14 are specially-designed high voltage transistors which are very difficult to manufacture along with lower voltage logic transistors which are integrated on the same integrated circuit (IC) substrate. Therefore, the conventional EEPROM of FIG. 1 is disadvantageous in that the transistors 14 must be specialized high voltage transistors and that these high voltage transistors must be integrated with other lower voltage transistors on a single substrate which often results in reduced yield.
In addition, the circuit of FIG. 1 contains seventeen transistors in order to store eight bits of information. Due to the use of seventeen transistors, a conventional EEPROM cell as illustrated in FIG. 1 will have a very large surface area compared to alternative solutions.
One other prior art device which is of interest contains multiple control gates, but does not use tunneling in order to store a logic value. This structure is referred to as a neuron MOSFET. A neuron MOSFET is a multi-control electrode device which operates based on capacitive coupling and does not use electron tunneling or hot carrier injection (HCI) of electrons into a floating gate in order to store a logic value. Instead, a neuron MOSFET is more like a conventional logic gate, and less like an EPROM or EEPROM cell, in that the neuron MOSFET is not a non-volatile structure but a structure that losses logic state when power is removed from the control gates. Therefore, a neuron MOSFET does not require a program and erase cycles and will not store a logic bit value in a non-volatile manner similar to conventional EEPROM cells.
Therefore, a new transistor structure which is non-volatile in nature and: (1) has a reduced surface area; (2) has a lower drain voltage to reduce gate oxide stress; and (4) has no need for high voltage transistors in the memory array which have been shown to reduce conventional yield, is needed in the IC industry.